Abstract:Aiming at the design requirements of high performance, high reliability, low cost and miniaturization for the spacecraft lower computer, combined with mature aerospace design experience and the application charac-teristics of Commercial Off-The-Shelf (COTS) devices, a design scheme of spacecraft lower computer system with dual industrial-grade SOC chips C8051F040 as the core, adopting dual-machine cold backup and sin-gle-machine dual-processor parallel operation architecture is proposed. The core idea is to make full use of the hardware resources built into the chip, reduce the types and quantity of external expansion components, thereby effectively reducing the hardware cost and PCB wiring difficulty of the lower computer, and realizing the miniaturization design goal; the dual processors realize high-speed information interaction and real-time working status monitoring through the built-in IIC bus, and combine software and hardware collaborative design to construct a hierarchical fault autonomous monitoring and recovery strategy of "single-processor self-inspection - dual-processor mutual inspection - satellite-level monitoring", which significantly improves the fault tolerance and rapid fault handling capability of the system. Test verification shows that the design increases the analog acquisition capability by 116% and the command output capability by 100% compared with the traditional single-processor design, and realizes the full redundancy design of the CAN bus; when one processor fails, the other processor can take over the work seamlessly to complete all telemetry acquisition and key command execution, ensuring that the core functions of the system are not interrupted. At present, this design has been applied on 6 satellites in orbit for more than 10 years, with stable in-orbit working status, which fully meets the actual application requirements of the spacecraft lower computer and has high engineering application value and promotion prospect.
