基于CICQ交换结构的低功耗研究与设计

Research and Design of Low-Power Techniques Based on the CICQ Switching Fabric

摘要:

针对高性能交换芯片在先进工艺下面临的功耗问题，基于CICQ交换结构开展低功耗技术研究；分析CMOS集成电路中动态功耗与静态功耗的来源，明确优化方向；采用改进的输出总线缓存设计与流控反馈机制，解决多端口数据突发场景下的队头阻塞问题；通过实施门控时钟、门控电源与多电压域技术，建立覆盖端口组、存储单元及SerDes接口的精细化功耗管理方案，并基于UPF标准构建从逻辑综合到物理实现的完整低功耗设计流程；实验结果表明，在12端口×4工作模式及12.5 Gbps单通道速率条件下，该方案使芯片总功耗由9.345 W降至5.520 W，降幅达40.9%，其中内部功耗降低48.2%，开关功耗降低46.5%，静态功耗降低33.4%。该方法能够满足高性能交换芯片的功耗控制需求，为同类型通信芯片的低功耗设计提供有效解决方案。

Abstract:

To address the power consumption challenges faced by high-performance switch chips in advanced process technologies, this study conducts research on low-power techniques based on the Combined Input and Crosspoint Queued (CICQ) switch architecture. It analyzes the sources of dynamic and static power consumption in CMOS integrated circuits to identify optimization directions. By employing an enhanced output bus buffer design and a flow control feedback mechanism, the issue of head-of-line blocking in multi-port data burst scenarios is resolved. Through the implementation of clock gating, power gating, and multi-voltage domain techniques, a refined power management scheme covering port groups, memory units, and SerDes interfaces is established. Additionally, a complete low-power design flow from logic synthesis to physical implementation is constructed based on the Unified Power Format (UPF) standard. Experimental results show that under a configuration of 12 ports × 4 operating modes and a single-channel data rate of 12.5 Gbps, this approach reduces the chip’s total power consumption from 9.345 W to 5.520 W, achieving a reduction of 40.9%. Specifically, internal power consumption is reduced by 48.2%, switching power consumption by 46.5%, and static power consumption by 33.4%. This method effectively meets the power control requirements of high-performance switch chips and provides a viable low-power design solution for similar communication chips.