基于FPGA的组合鉴频鉴相设计与验证

Design and Verification of Combined Frequency and Phase Discrimination Based on FPGA

摘要:

为实现锁相解调设备鉴相数字化，研究了计数鉴频器、门电路锁相器、RS触发计数鉴相器，采用周期计数测频、异或门鉴相、RS触发计数鉴相相结合的方法实现鉴相数字化，提出了锁相解调器总体设计方案，开展锁相解调设备数字信号处理硬件设计，完成了异或门鉴相、RS触发计数和数字融合鉴相设计的试验验证。结果表明，数字鉴频鉴相融合设计方法便于融入数字信号处理设计，节省了鉴相器的硬件成本，并增加了数字鉴频功能，提升了产品的截获性能。

Abstract:

To achieve phase locked demodulation equipment by using Digital, this article investigates Gate circuit phase-locked device and RS trigger counting phase-locked device. Combined methods is proposed of cycle counting frequency measurement, XOR gate phase detection and RS trigger counting phase-locked detection. Composition principles block diagram of phase locked demodulation equipment is elaborated on detail. Digital signal processing hardware of phase locked demodulation equipment is designed on detail and verified by experiments. The results indicate that the combined methods is easy to integrate design of digital signal processing design. Hardware costs for phase discriminators are saved, digital frequency discrimination function is increased, and produce interception performance is improved.