基于FPGA的高能效YOLO目标检测系统

High Energy Efficiency YOLO Target Detection System Based On FPGA

摘要:

依据YOLO系列网络在目标检测领域的出色表现，提出了一种基于FPGA的高能效YOLO目标检测系统，通过对YOLOv5n网络进行层融合优化模型，并采用量化感知训练对网络模型进行再训练和量化，将特征图和权重数据量化为8位，降低了硬件资源的消耗；设计了一种混合流可配置的硬件加速器架构，通过配置模型参数实现网络层的前向推理，在硬件模块中对网络层进行优化设计，并采用乒乓双缓存与层间流水线协同设计；整个硬件加速系统通过软硬件协同设计实现，合理调度硬件模块，实现了软核处理器与硬件加速器高效并行工作；经实际测试在Xilinx VC707 FPGA开发板上，系统以100 MHz的工作频率实现了27.15 GOPS的吞吐量，功耗仅为2.88 W，实现了9.43 GOPS/W的高能效，兼顾了检测速度和功耗，满足目标检测的需求。

Abstract:

Based on the excellent performance of YOLO series networks in the field of target detection, a high-efficient YOLO target detection system based on FPGA is proposed. The YOLOv5n network is optimized by layer fusion, and the network model is retrained and quantized using quantization aware training. The feature map and weight data are quantized to 8 bits, reducing hardware resource consumption. A hybrid flow configurable hardware accelerator architecture is designed to realize the forward inference of the network layer by configuring model parameters. The network layer is optimized in hardware module, and ping-pong dual cache and interlayer pipeline is adopted. The entire hardware acceleration system is implemented through coordinated software-hardware design, and hardware modules are reasonably scheduled to achieve efficient parallel work of soft-core processor and hardware accelerator. Through practical test on Xilinx VC707 FPGA development board, the system achieves the throughput of 27.15 GOPS at the operating frequency of 100 MHz, and the power consumption is only 2.88 W, achieving a high energy efficiency of 9.43 GOPS/W, balancing detection speed and power consumption, and meeting the requirements of target detection.