基于Farrow架构的任意倍重采样的FPGA设计与实现

FPGA Designe and Implementation of Arbitrary Multiple Resampling Based on Farrow Architecture

摘要:

任意波形发生器通常使用直接数字波形合成技术生成任意波形，然而使用此技术实现可变采样率功能时，需要调整时钟的工作频率，导致输出中存在难以滤除的镜像频率以及硬件实现难度增加；针对上述问题，对基于Farrow架构的任意倍重采样方法进行了研究，在FPGA上进行了固定时钟驱动下的32路并行的任意倍重采样的逻辑设计与实现；并针对逻辑实现中出现的量化误差积累问题，提出了清除累积误差的逻辑实现方案；经实验测试，实现了在187.5MHz固定时钟驱动下1KSPS~6GSPS范围的采样率转换，并解决了量化误差积累造成的长时间运行时波形失真的问题。

Abstract:

Arbitrary waveform generators typically employ direct digital waveform synthesis techniques to generate arbitrary waveforms. However, when utilizing this technology to achieve a variable sampling rate functionality, adjustments to the clock frequency can introduce hard-to-filter image frequencies and increase the complexity of hardware implementation. To address these issues, research was conducted on an arbitrary multiple resampling method based on the Farrow architecture. A parallel implementation of a 32-channel arbitrary resampling system was designed and realized on an FPGA under a fixed clock drive. Additionally, a solution for managing the accumulation of quantization errors in the logical implementation was proposed and implemented. Experimental results demonstrated that the system achieved sampling rate conversion from 1KSPS to 6GSPS under a fixed clock frequency of 187.5 MHz and effectively addressed waveform distortion issues caused by quantization error accumulation during long-term operation.