基于UVM的片上网络验证平台设计

Design and Implementation of a Synchronization Network Verification Platform based on UVM

摘要:

同步网络是片上网络(Network on Chip,NoC)的一种,网络上的通信情景复杂多变,而传统的验证平台存在输入定向,验证层次不规范,验证的覆盖率不足等问题,难以应付此类要求较高的功能验证场景。为解决此问题,构建了一个基于通用验证方法学(Universal Verification Methodology,UVM)的验证平台,并设计验证方案,采用约束随机测试为主,辅以定向测试的方式进行验证。此方法既可以保证输入的正确性,又可以提高验证效率,使验证更为全面。该平台不仅规范了验证流程,还实现了输出结果的自动比对,使验证流程更加自动化。此外,根据设计的功能需求,编写了覆盖组和交叉覆盖组来进行覆盖率的收集,以便量化验证进度。经过仿真后功能覆盖率达到100%,代码覆盖率达到87.62%,符合实验预期。

Abstract:

The synchronous network is a type of network on chip (NoC), where communication scenarios are complex and varied. However, traditional verification platforms have problems such as input orientation, non-standard verification levels, and insufficient verification coverage, making it difficult to cope with such demanding functional verification scenarios. To address this issue, a verification platform based on Universal Verification Methodology (UVM) was constructed, and a verification scheme was designed using constrained random testing as the main approach, supplemented by directed testing for verification. This method can ensure the correctness of input and improve verification efficiency, making verification more comprehensive. This platform not only standardizes the verification process, but also achieves automatic comparison of output results, making the verification process more automated. In addition, according to the functional requirements of the design, coverage groups and cross coverage groups were written to collect coverage rates for quantitative verification progress. After simulation, the functional coverage rate reached 100%, and the code coverage rate reached 87.62%, which met the experimental expectations.