面向主动降噪验证的AD/DA测试平台设计

ADDA Test Platform Design Based on ANC Verification

摘要:

针对主动降噪（ANC，Active Noise Cancellation）算法程序调试难度大、相关滤波器结构可视化程度差、硬件平台底噪大的问题，设计了一款底噪小、程序可视化程度高、搭建模型简单的ADDA硬件验证平台(AKM平台)。相比较传统的ANC调试过程，AKM平台在降噪算法验证过程中不需要编写程序，仅需要基于Simulink HDL模块化工具搭建仿真模型，生成Bitstream文件，将其烧录到验证平台即可实现算法的验证，有效避免了开发者编写和调试程序过程的复杂性，最终实现了一款操作高效的ANC算法验证平台。实验结果表明，该系统在输入激励信号为1KHz 100mV，采样率为32 KHz 24bit的条件下，测试输出信号的总谐波失真为0.005217%；信噪比为98.295 dB。在不输入任何激励信号的情况下，系统平台的底噪为5.360 uVrms。

Abstract:

Aiming at the problems of difficult debugging of active noise cancellation (ANCActive Noise Cancellation) algorithm program, poor visualization of the related filter structure, and large bottom noise of the hardware platform, an ADDA hardware validation platform (AKM platform) with small bottom noise, high program visualization, and easy to build model is designed. Compared with the traditional ANC debugging process, the AKM platform does not need to write a program during the verification of the noise reduction algorithm, but only needs to build a simulation model based on the Simulink HDL modularization tool, generate a Bitstream file, and then burn it into the verification platform to realize the verification of the algorithm, which effectively avoids the complexity of the process of the developer"s writing and debugging procedures, and ultimately realizes an operationally efficient ANC algorithm verification platform. The final result is the realization of an efficient ANC algorithm verification platform. The experimental results show that the total harmonic distortion of the output signal is 0.005217% and the signal-to-noise ratio is 98.295 dB under the conditions of 1KHz 100mV input signal and 32 KHz 24bit sampling rate, and the noise floor of the platform is 5.360 uVrms without any input signal.