基于 FPGA 的深度可分离卷积加速器研究

Research on depth-separable convolution accelerators based on FPGA

摘要:

设计了一种基于FPGA的低功耗深度可分离卷积加速核；根据PW卷积和DW卷积计算中的共性，采用一种固定乘法阵列通过改变特征和权重输入数据流的方式实现两种卷积的计算结构，最大化DSP的利用率；针对8位非对称量化中符号位可能会溢出的问题，采用符号位单独处理的方法重新封装了双乘法器结构；通过层内7级流水结构保证每个周期数据处理的并行度；在Zynq UltraScale+系列FPGA上成功部署了加速结构；经实验测试，提出的加速结构在提高网络推理速度的同时降低了片上资源的依赖度和整体功耗，原生MobilenetV2在所提FPGA加速器上的平均吞吐率高达130.6GOPS且整体功耗只有4.1w，满足实时边缘计算的要求；相比其他硬件平台，能效比有明显提升；与FPGA上的同类型加速器相比，在性能密度（GOPS/LUT）、功率效率（GOPS/W）和DSP效率（GOPS/DSP）上均有优势。

Abstract:

A low power deep separable convolution accelerator kernel based on FPGA is designed. According to the commonality of PW convolution and DW convolution calculation, a fixed multiplicative array is used to realize the two convolution calculation structures by changing the feature and weight input data stream, so as to maximize the utilization of DSP. In order to solve the problem that the sign bit may overflow in 8-bit asymmetric quantization, the double multiplier structure is repackaged by using the sign bit processing method. The parallelism of data processing in each cycle is guaranteed by the 7-level pipelining structure in the layer. Successfully deployed the accelerator structure on the Zynq UltraScale+ series FPGA; The experimental results show that the proposed acceleration structure can improve the inference speed of the network and reduce the dependence of on-chip resources and the overall power consumption. The average throughput of the original MobilenetV2 on the proposed FPGA accelerator is as high as 130.6GOPS and the overall power consumption is only 4.1w, which meets the requirements of real-time edge computing. Compared with other hardware platforms, the energy efficiency ratio is significantly improved; Compared with the same type of accelerator on FPGA, it has advantages in performance density (GOPS/LUT), power efficiency (GOPS/W) and DSP efficiency (GOPS/DSP).