基于UVM的片上网络路由器验证平台

Verification Platform for Network-on-Chip Router Based on UVM

摘要:

路由器是片上网络的关键组件,其性能对于整个网络的性能具有重要影响；针对片上网络路由器进行功能验证,采用SystemVerilog和自动化脚本搭建了基于通用验证方法学(UVM)的验证平台,简化了验证流程；在验证平台中,通过划分多个agent向路由器的每个端口发送受约束的随机激励和定向测试序列,并创建了多个独立的测试用例,对路由器的功能进行充分的验证；通过运用覆盖率驱动策略,对验证进程进行了量化；根据路由器的设计要求,编写了覆盖组和交叉覆盖组以收集覆盖率数据；此验证平台已应用于人工智能芯片的验证工作,平台中的组件和测试用例均可实现更高层次的复用；此外,通过VCS和Verdi的联合仿真,实现了100%的功能覆盖率和95.6%的代码覆盖率的目标。

Abstract:

The router is a key component of the on-chip network, and its performance has an important impact on the performance of the whole network. For the functional verification of the network-on-chip router, a verification platform based on the universal verification methodology (UVM) is constructed by using SystemVerilog and automation scripts to simplify the verification process. In the verification platform, the router's functionality is adequately verified by dividing multiple agents into sending to each of its ports constrained random excitation and directional tests, and creating multiple independent test cases to fully verify the functionality of the router. The verification process is quantified by applying coverage-driven strategies. Coverage groups and cross-coverage groups are written to collect coverage data according to the design requirements of the router. This verification platform has been used in the verification of AI chips, and both the components in the platform and the components and test cases in the platform can be reused at a higher level. In addition, the goal of 100% functional coverage and 95.6% code coverage is achieved through the simulation of VCS and Verdi.