基于CPU+FPGA的实时临空信道模拟器设计

Design of Real Time Near Space Channel Simulator Based on CPU+FPGA

摘要:

信道建模是研究临近空间通信技术、评估系统传输特性的基础和重要方法。临近空间飞行器从低速向高速发展,信道变化频次随飞行器速度增大而愈加频繁。为实现对临空通信过程中信道衰落的实时仿真,研制基于中央处理器(Central Processing Unit,CPU)和现场可编辑门阵列(Field-Programmable Gate Array,FPGA)架构、参数1 ms更新一次的临空信道模拟器。该模拟器内置气象性损耗模型和无线信道衰落模型,CPU端通过设计状态机控制模块、优化参数计算逻辑、优化操作系统来压缩信道参数的计算时间。FPGA部分设计关键信息同步方案、基于状态机的双保障更新机制保证参数的可靠稳定传输、并行加速处理实现信息交互和增强信号处理速度。实测结果表明,上述方案有效提升了临空信道模拟器的参数计算速度和信号处理速度,可实现信道参数随收发机运动1 ms更新一次。

Abstract:

Channel modeling is the foundation and important method for studying near space communication technology and evaluating system transmission characteristics. Near space vehicles are developing from low speed to high speed, and the frequency of channel changes increases with the increase of aircraft speed. To achieve real-time simulation of channel fading in near space communication, a near space channel simulator based on the Central Processing Unit (CPU) and Field Programmable Gate Array (FPGA) architecture with parameters updated every 1 ms is proposed. The simulator has a built-in meteorological loss model and a wireless channel fading model. The CPU compresses the calculation time of channel parameters by designing a state machine control module, optimizing parameter calculation logic, and optimizing the operating system. Design key information synchronization scheme for FPGA, dual guarantee update mechanism based on state machine to ensure reliable and stable parameter transmission, parallel acceleration processing to achieve information exchange and enhance signal processing speed. The actual measurement results show that the above scheme effectively improves the parameter calculation speed and signal processing speed of the near space channel simulator, and can achieve channel parameters to be updated once every 1 ms with the movement of the transceiver.