基于嵌入式结构半导体芯片信息测试系统平台设计

Design of information testing system platform for semiconductor chip based on embedded structure

摘要:

为解决因半导体芯片信息平均压缩比较大而导致的信息测试时间过长的问题,设计基于嵌入式结构半导体芯片信息测试系统平台。根据嵌入式终端体系布局形式,建立LeNet网络模型,再以此为基础,完善SMTExecutor结构的执行流程,实现信息测试系统平台的工具集模块设计。分别定义Deflate机制、LZ4机制,联合数据信息参量,规范系统平台同步化线程的执行模式,实现对半导体芯片信息的处理。按照嵌入式结构定义标准,生成配置文件,通过导入关键信息的方式,规划量化测试条件,从而对命令词进行识别,实现对测试系统功能的优化,联合工具集模块,完成基于嵌入式结构半导体芯片信息测试系统平台的设计。实验结果表明,上述系统平台的应用,可以在数据导入过程中解决半导体芯片信息平均压缩比过大的问题,能够大幅缩短信息测试时间,符合实际应用需求。

Abstract:

In the process of data import, in order to solve the problem that the information test time is too long due to the large average compression ratio of semiconductor chip information, a semiconductor chip information test system platform based on embedded structure is designed. According to the layout of the embedded terminal system, the LeNet network model is established. On this basis, the execution process of the SMTExecutor structure is improved, and the tool set module design of the information test system platform is realized. Define Deflate mechanism and LZ4 mechanism respectively, combine data information parameters, standardize the execution mode of system platform synchronization thread, and realize the processing of semiconductor chip information. According to the embedded structure definition standard, the configuration file is generated, and the quantitative test conditions are planned by importing the key information, so as to identify the command words, realize the optimization of the test system function, and complete the design of the embedded structure semiconductor chip information test system platform by combining the tool set module. The experimental results show that the application of the above system platform can solve the problem that the average compression ratio of semiconductor chip information is too large in the process of data import, and can greatly shorten the information test time, which meets the actual application requirements.