10-26GHz CMOS六位数控衰减器设计与实现

Design and realization of a 10 ~ 26 GHz CMOS 6-bits digital attenuator

摘要:

为了使衰减器更好的适应相控阵系统对高集成度波束赋形电路的应用需求。基于55nm CMOS工艺，设计了一款具有低插入损耗、低附加相移特性的六位数控衰减器，该数控衰减器采用桥T和π型衰减结构级联而成，在10-26 GHz频率范围内实现步进为0.5dB、动态范围为0-31.5 dB的信号幅度衰减。为减小插入损耗,NMOS开关采用悬浮栅和悬浮衬底连接方式，同时采用了电容补偿网络和电感补偿以有效降低附加相移。仿真结果表明，在10-26GHz的频带范围内，该数控衰减器的插入损耗小于-7dB，输入/输出回波小于-10dB，附加相移小于±3°，所有衰减态的衰减误差均方根小于0.8dB，芯片的核心电路面积为0.36 mm×0.16 mm。

Abstract:

In order to reduce the influence of RF singal on the performance of attenuation circuit in transceiver component,the attenuator can better adapt to the application requirements of high integration beamforming circuit in phased array system. This paper presents a 6-bits digital attenuator featuring small phase variation and low insertion loss using a 55-nm CMOS technology. The digital attenuator had a dynamic attenuation range from 0 to 31.5dB with a step resolution of 0.5dB. In order to reduce the insertion loss, the floating gate and floating body is adopted in the NMOS switch. In addition, low phase variation is achieved by using inductance compensation as well as capacitance compensation network. The simulation results shows that the insertion loss is less than -7 dB, while achieving an ±3°phase variation for all attenuation state in the frequency range of 10~ 26 GHz. The input and output reflection wave are less than -10dB. The RMS(Root Mean Square) attenuation error is less than 0.8dB. The total chip size excluding pads is 0.36mm× 0.16mm (mm2).