基于DPI-C的脉动阵列模块验证平台

Systolic array module verification platform based on DPI-C

摘要:

针对卷积神经网络加速器中有关于脉动阵列模块的验证，提出并实现了一种基于直接编程接口C（DPI-C，Direct Programming Interface C）程序的验证平台，采用内嵌DPI-C程序并利用通用验证方法学（UVM，Universal Verification Methodology）满足脉动阵列模块中的浮点数乘加运算的验证需求。实验利用了SystemVerilog中的DPI接口技术，在验证平台中实现对C或C++代码的调用，通过编写C函数来实现复杂的参考模型，浮点数乘加运算便是利用C代码编写的。验证平台的整体结构是根据UVM来设计的，其中包括激励的设计、参考模型的编写、数据校对等组件，整个验证平台高效、简洁。此平台已经应用于人工智能芯片的验证工作中，编写的测试用例可以对脉动阵列进行充分验证，覆盖率达到了100%。验证平台可以保证脉动阵列验证的全面性、高效性并且调试纠错简单方便，同时还实现了UVM环境和测试用例的重用。

Abstract:

Aiming at the verification of the systolic array module in the convolutional neural network accelerator, a verification platform based on the direct programming interface C (DPI-C) program is proposed and implemented. The embedded DPI-C program is used and the universal verification methodology (UVM) is used to meet the verification requirements of floating-point multiplication and addition in the systolic array module. The experiments take advantage of the DPI interface technology in SystemVerilog to implement calls to C or C++ code in the verification platform. Complex reference models are implemented by writing C functions, and floating-point multiplication and addition operations are written using C code. The overall structure of the verification platform is designed according to UVM, which includes the design of excitation, the writing of reference model, data proofreading and other components, and the whole verification platform is efficient and concise. The platform has been applied to the verification of artificial intelligence chips, and the test cases written can fully verify the pulsating arrays with 100% coverage. The verification platform ensures comprehensive and efficient verification of systolic arrays and easy debugging and error correction, and also enables reuse of the UVM environment and test cases.