基于正弦数据压缩算法的DDS研究及FPGA实现

Research on DDS based on sinusoidal data compression algorithm and FPGA implementation

摘要:

针对直接数字频率合成器（DDS）芯片因存储空间开销大导致功耗增加,可靠性降低的问题 ,设计了一种将改进sunderland算法与QE-ROM技术相结合的一种用于直接数字频率合成器（DDS）的紧凑型16位精度正弦查找表(ROM)；对所设计的正弦查表算法进行了系统级仿真与硬件描述语言（Verilog HDL)实现，并最终在FPGA上进行了整体算法功能与性能的验证；基于AD5360芯片制作了一款多通道16位输出数模转换器(DAC),并搭载降压稳压芯片LM317和LM337实现了一款可以将220V工频转换为DAC所需的±9V和3.75V的供电电源。测试结果显示，设计的正弦查找表算法在达到16位精度的同时，只占据8576bit的存储空间。所使用的正弦数据优化算法相比较传统的DDS正弦波形发生器资源节省99.2%，实现了122：1的压缩比，有效降低了DDS的芯片面积和功耗；

Abstract:

A compact 16-bit precision sine lookup table (ROM) for direct digital frequency synthesizer (DDS) is designed by combining the improved sunderland algorithm with QE-ROM technology, and the system-level simulation and hardware description language (Verilog HDL) implementation of the designed sine lookup table algorithm are carried out. The designed sine lookup algorithm is simulated and implemented in hardware description language (Verilog HDL), and the overall algorithm function and performance are finally verified on FPGA; a multi-channel 16-bit output digital-to-analog converter (DAC) is fabricated based on AD5360 chip, and a step-down voltage regulator LM317 and LM337 are equipped to realize a power supply that can convert 220V industrial frequency to ±9V and 3.75V required by DAC. 3.75V power supply. The test results show that the designed sinusoidal lookup table algorithm occupies only 8576 bits of storage space while achieving 16-bit accuracy. The sine data optimization algorithm used saves 99.2% of resources compared to the conventional DDS sine waveform generator, achieves a compression ratio of 122:1, and effectively reduces the chip area and power consumption of the DDS.