基于UVM的远程控制FPGA一体化闭环仿真验证平台

Design of Remote Control FPGA ?closed-loop simulation Verification Platform Based on UVM

摘要:

远程控制FPGA是卫星执行地面指令和转发地面数据的核心部分，必须对其进行全面验证，避免存在设计隐患。本文以远程控制FPGA为被测件，使用目前最先进性的通用验证方法学UVM建立了一体化闭环仿真验证平台。该验证平台具有带约束收敛的测试向量随机生成和自动检查输出结果正确性功能，实现了功能覆盖率检测，能有效提高远程控制FPGA验证的效率和质量，较好的满足了验证需求。

Abstract:

Remote control FPGA is the core part of satellite executing ground instruction and transmitting ground data, so it must be verified comprehensively to avoid potential design problems.??In this paper, remote control FPGA as the Device Under Test, using the most advanced Universal Verification Methodology UVM to establish an integrated closed-loop simulation verification platform.??The verification platform has the functions of random generation of test vector with constraint convergence and automatic checking of the correctness of output results, realizing the function coverage detection, which can effectively improve the efficiency and quality of remote control FPGA verification and better meet the verification requirements?.