高速数字信号测试完整性分析与研究

Signal Integrity Analysis and Research of High Speed Digital Signal Test

摘要:

雷达高速数字电路模块(基于VPX总线)的高速数字接口测试过程中,针对出现的高速数字信号质量不理想的问题,分析了该现象出现的原因并最终提出了保证测试过程中高速信号的信号完整性的解决方案：在高速信号连接电路设计中避免出现多个终端输出。实验结果表明,高速信号接口单一输出端的高速信号质量相比多个输出端的信号质量有明显改善,信号误码率优化了e_¹⁰倍；通过眼图测量,信号速率为1.25Gbps时单一输出端的高速信号眼高为8.9uW,眼宽为730ps,多个输出端的信号已经无法形成眼图。验证了高速数字信号测试时为了保证信号完整性应避免出现多个终端输出的正确性。

Abstract:

In order to solve bad quality problem of high speed digital signal, in radar high speed digital circuit module(based on VPX bus)’s high speed digital interface testing, it analyzes the reason and introduces a solution to keep signal integrity of high speed signal in testing. It is avoiding multi-output in high speed signal connection circuit. Experimental results show that high speed signal quality of single-output interface is much better than multi-output interface. The signal error rate is improved e_¹⁰ times. Through Eye-diagram measure, for 1.25Gbps signal rate testing, single-output high speed signal eye height is 8.9uW, eye width is 730ps. However, multi-output signal cannot form an eye figure. All above validate that to ensure signal integrity in high speed digital signal testing should avoid multi-output.