FPGA块存储器的多位翻转容错设计

Multiple Bit Upset Fault Tolerance Design of FPGA Block Memory

摘要:

在高可靠性航空航天、航空电子设备和军用应用中，辐射引发的多比特翻转(MBU)成为FPGA存储器的一个主要的可靠性问题。传统的单比特错误纠正(SEC) 和双比特错误检测(DED) 无法对FPGA存储器发生的MBU故障提供防护，引发存储器的存储故障。为了减少MBU造成的影响，利用RM(2,5)编码对FPGA块存储器进行防护,实现了单个码字小于4位的翻转错误的纠正。对RM编码系统进行了三模冗余设计，解决了RM码不具备抗辐射的缺陷。设计的RM(2,5)编译码模块在 Xilinx Virtex-5 FPGA中实现，编码模块频率以225.284MHz运行，占用LUT资源1.33%。通过理论分析和硬件实验表明，该错误检测与纠正(EDAC)系统能够纠正4位以下的翻转，提高FPGA存储器的可靠性。

Abstract:

In high-reliability aerospace, avionics and military applications, radiation-induced multiple bit upset (MBU) has become a major reliability concern in FPGA memory cells. Traditional single-bit error correction (SEC) and double-bit error detection (DED) cannot provide protection against MBU fault in FPGA memory, causing memory storage failures. In order to reduce the impact of MBU, the RM(2,5) encoding is used to protect the FPGA block memory，which realizes the correction of the flip error of a single codeword less than 4 bits. The RM coding system is designed with triple module redundancy (TMR), which solves the defect that the RM code does not have radiation resistance. RM(2,5) codec module has been implemented in Xilinx Virtex-5 FPGA and the codec module runs at 225.284MHz, which only 1.33% LUT resource occupation. Theoretical analysis and hardware experiments show that the Error Detection And Correction(EDAC) system can correct errors of less than 4 bits and improve the reliability of the FPGA memory.