基于CPLD芯片控制的视频图像处理系统设计

Design of video image processing system based on CPLD chip control

摘要:

针对当前连续视频图像的空间冗余性较高，图像数据处理及时性较差的问题，设计了基于CPLD芯片控制的视频图像处理系统。将CPLD存储模块内提取的数据信息，平均分配至视频图像采集元件及图像边缘检测元件中，再借助信息传输信道，建立与VGA视频图像显示模块的物理连接，实现视频图像处理系统的硬件执行方案设计。利用分数像素差优化结果，规范子窗口的动态显示权限，控制连续视频图像在空间范围内的冗余化程度，完成图像源路数的智能控制处理。联合视频进程与多线程控制原理，实施数据包缓冲区的信息排序，再建立全新的视频流存储模式，实现视频流的完整播放。对比实验结果表明，与多路视频处理手段相比，应用CPLD芯片控制处理系统后，图像数据帧缓存速率明显提升，而VGA信息转换指标却大幅下降，在抑制连续视频图像空间冗余能力的同时，解决了图像数据处理不及时的问题。

Abstract:

Aiming at the problems of high spatial redundancy of current continuous video images and poor timeliness of image data processing, a video image processing system based on CPLD chip control is designed. The data information extracted from the CPLD storage module is evenly distributed to the video image acquisition element and the image edge detection element, and then the physical connection with the VGA video image display module is established by means of the information transmission channel to realize the hardware execution plan of the video image processing system design. Use the optimized result of fractional pixel difference to regulate the dynamic display permission of the sub-window, control the degree of redundancy of continuous video images in the spatial range, and complete the intelligent control processing of the number of image sources. Combined with the video process and multi-threaded control principle, the information order of the packet buffer is implemented, and then a brand new video stream storage mode is established to realize the complete playback of the video stream. The comparison experiment results show that, compared with the multi-channel video processing method, after applying the CPLD chip to control the processing system, the frame buffer rate of image data is significantly increased, while the VGA information conversion index is greatly reduced, while suppressing the spatial redundancy of continuous video images. , Solve the problem of image data processing is not timely.