基于IBIS模型的多路脉冲信号源ADS仿真

ADS Simulation of Multi-channel pulse Signal Source Based on IBIS Model

摘要:

使用高速比较器+两级时钟扇出buffer+比较器输出CMOS电平方案,利用ADS的Integrity–IBIS模块,搭建了80台示波器用脉冲信号源。介绍了IBIS模型原理、语法结构及模型适用性,并进行了瞬态仿真,分析了高速比较器IC、时钟扇出IC和脉冲输出IC之间的差分信号完整性,对最终输出信号的延迟和抖动进行了计算。仿真结果表明：使用高速比较器+两级时钟扇出buffer+比较器输出CMOS电平方案可获得80路同步触发信号；输入输出信号延迟<2.6ns,抖动<11ps,50Ω负载时输出信号幅值1.97V,前沿997ps,满足多路示波器外触发信号要求。

Abstract:

Based on the application of level scheme of CMOS with high-speed comparator, two-stage clock fan-out buffer and comparator output, the integrity-IBIS module of ADS was adopted to build up 80 oscilloscope external trigger systems . The principle, grammar structure and applicability of IBIS model was introduced, the transient simulation was carried out to analyze the integrity of differential signals between the high-speed comparator IC, clock fan-out IC and pulse output IC, and the delay and jitter of the final output signal were calculated. The results of the simulation showed that: 80 channel synchronous trigger signal could be achieved with the application of level scheme of CMOS with high-speed comparator, two-stage clock fan-out buffer and comparator output; the delay of input and output signal was less than 2.6ns and the jitter was less than 11ps, output signal amplitude was 1.97V and the leading edge was 997ps with the load of 50Ω, which met the requirements of external trigger signals of the multi-channel oscilloscope.