基于FPGA的通用可编程雷达接收机控制系统设计

Design of General Programmable Radar Receiver Control System Base On FPGA

摘要:

针对不同雷达接收机测试时对不同定时时序及总线控制的需求，文中提出了一种基于FPGA的通用可编程雷达接收机控制系统设计方法，该方法采用可编程门阵列（FPGA）器件实现多路定时时序、总线控制及数据传输的功能，定时精度可达0.01us，总线速率可达100M；对接收机接口进行研究，采用软件柔性配置和适配电缆匹配的方式实现对多型接收机的控制。实验结果表明，该系统可以实现多型接收机控制，达到设计要求。该系统还可以应用于其他设备的控制，具有良好的通用性和可扩展性。

Abstract:

In view of the needs of the different timing sequence and bus-mastering at the different radar receivers testing , this paper presents a universal design method of radar receiver control system based on FPGA,The method adopts FPGA to realize the function of multi timing signals、bus-mastering and data transmission，the timing accuracy can reach 0.01us，the bus speed can reach 100M. Throngh the study of the receivers’interface ,It also realizes the control of multi type receivers through software flexible configuration and matching with different adaptable cables. Experimental results show this system can implement the control of multi type recivers ,reaches the request of design. The control system can also be applied to the control of other devices ,and has good versatility and expansibility.