一种新型的FPGA实现RS422串口通信方法

A New Method of RS422 Serial Port Communication Based on FPGA

摘要:

在FPGA实现RS422串口通信的常用方法中经常遇到诸多问题,如FIFO深度读取不正确、FIFO写数据端口与读数据端口时序竞争、多个模块间信号延时导致FPGA亚稳态等问题,因此设计了一种新型的RS422串口通信实现方法;该方法通过利用寄存器数组作为循环缓存代替FIFO,利用计数器代替传统的波特率产生模块,把常用方法中的多个模块整合成一个模块,只采用一个主时钟,所有寄存器的时钟输入端共享一个时钟,对FPGA逻辑与时序进行了有效约束,避免了FPGA中亚稳态产生;试验结果表明该方法实现的RS422串口通信高速、可靠、稳定,并且利用FPGA实现RS422串口通信,可使整个系统更为灵活、紧凑,减小整个电路的体积,提高系统的可靠性和稳定性。

Abstract:

The common method of RS422 serial port communication realized by FPGA often encounter many problems, such as FIFO depth is incorrect, the timing of writing FIFO data port and reading FIFO data port are compete, and signal delay between multiple modules leads to FPGA metastable state, so a new method of RS422 serial port communication is proposed. This method replaces the traditional FIFO by using register array as a cyclic queue, uses the counter instead of the baud rate generation module, integrate multiple modules into one module, only one master clock, all registers share one clock with the clock input, and constraints FPGA logic and timing to avoid the FPGA metastable state. The experimental results show that the method is fast, reliable and stable. It can make the whole system more flexible and compact, reduce the whole circuit volume and improve the reliability and stability of the system.