基于锁存器路径的静态时序分析在第三方验证中的应用

Application of Latch_Based STA analysis in Independent Verification

摘要:

随着可编程逻辑门阵列（FPGA）设计规模的扩大，静态时序分析可有效减轻时序仿真的负担，缩短项目周期。常见的静态时序分析(STA)多是基于触发器（FF_Based STA）,对触发器的STA算法研究已经比较成熟。但FPGA综合后网表可能会产生锁存器，而锁存器的STA与触发器的STA在算法上存在差异。为保证在FPGA产品第三方验证工作中对STA路径分析覆盖率达到100%，有必要对基于锁存器的时序分析（Latch_Based STA）做研究。阐述了锁存器“时间借入”与“时间借出”的概念。分析了“锁存器宽裕时间(slack time)”特性，绘制了其函数图。在某FPGA第三方验证项目中使用STA 工具Prime Time（一种计算机模型分析工具），分别对由“时间借入”、“时间借出”而导致“时序松弛”和“时序收紧”两种情况做了计算和分析，对STA路径分析覆盖率达到了100%，满足了第三方验证要求。

Abstract:

With the expansion of FPGA design scale,STA can relieve the stess of Timing Simulation,shorten project cycle.The common STA is more FF_Based STA,but after synthesis,unexpected Latch can be generated.While the calculating algorithms of Latch_Based STA and FF_Based STA is different,for the purpose of reaching 100% coverage rate of SAT path,it is necessary for the Independent Verification Authority to do some research on Latch_Based STA .The conception of “Time Borrowed”,”Time Given” and the feature of Latch slack time was explained,its function graphic was abstracted. Two separate example was given by Prime Time( a tool of Computer model simulation)