一种高可靠宇航控制器设计及可靠性评估

Design and Reliability Evaluation of Controller with High Reliability Used for Aerospace

摘要:

将8051、存储器等IP核集成在FPGA内部, 可实现宇航控制器高可靠、小型化的应用需求。但FPGA在空间环境中容易发生单粒子翻转事件(SEU),影响系统正常功能,常采用在FPGA内部进行三模冗余(TMR)设计;针对三模冗余系统无法纠正存储区中发生的SEU故障,提出了一种采用三模冗余架构并对FPGA配置区域进行刷新重载的解决方案,同时采用马尔可夫模型对该设计方案进行了可靠性评估和仿真;结果表明,采用该设计架构的宇航控制器具有较高的可靠性与安全性,可实现飞行器的长期稳定运行。

Abstract:

In order to meet the high-dependability requirement of electronic equipment for aerospace, a new method which integrating 8051 IP core and storage IP core into FPGA is proposed. After analyzing the shortcoming of traditional Triple Module Redundancy (TMR) design aiming to migrate the SEU effect on FPGA, a fault tolerance method based on TMR and readback-scrubing the configuration-data of FPGA is used. Then the reliability of this architecture is achieved in detail by Matlab tool with Markov model. Simulation results show that this FPGA architecture has higher reliability, which can meet the requirement of Aerospace electronic controller. 