基于SRIO传输的高速时钟电路的优化设计

An Design Optimization of High-speed Clock Circuit on SRIO transfers

摘要:

随着系统电路工作频率的不断越高,在应用中对系统互连和电路间的时钟提出了更高的要求。针对在某信号处理系统的设计中,在测试中偶尔出现SRIO链路异常问题,对高速时钟的参数进行了深入分析,发现了时钟信号受到热噪声的影响引起时钟抖动,会导致SRIO链路断开。提出了增加时钟信号的过渡斜率的优化方案,改善了时钟信号的品质,试验证明系统工作稳定可靠,达到了预期效果。

Abstract:

Owing to the increasing high frequency of circuit system,it is required the performance of clock signal transmission,applying to system interconnection an circuit.To deeply analysis on a High-speed clock circuit and parameter of a signal process system can not work properly and the SRIO link error in the process of testing, we find that Thermal Noise effects for clock signals,jitter affects the SRIO link disconnection. Therefore,thesis discuss t present solution for An Design Optimization,by increasing the transition slope of the clock signal,improve clock suplly quality and reliability function,in the last,the experiment results show that the system works stably and reliably,The proposed method achieves the expected effect.