基于ARM+FPGA的PLC计数器的设计

Design of Counter in PLC Based on ARM+FPGA

摘要:

计数器是PLC内部重要的软元件之一,在以PLC为核心部件的自动控制系统中,这种软元件通过相应的程序实现系统的实时准确的计数;ARM通过双口RAM发送指令命令给FPGA,FPGA控制计数器进行相关操作,FPGA的晶振工作频率50 MHz作为计数器控制模块的时序约束,设计的计数器具有加减计数功能、断电保持功能、数据回传功能等,以满足PLC控制器的计数需求,并通过使用地址映射存储器使得计数器控制器的指令执行更加高效;设计了计数器与FPGA指令执行控制器的通信协议;通过对设计完成后的仿真与测试,单个计数器的计数频率达到2 MHz,基本实现了PLC计数器的功能,并且达到了稳定计数的设计要求。

Abstract:

Counter is one of the important parts of the PLC. In the automatic control system with PLC as the core component, the software can realize the real-time and accurate count of the system. Through the dual port RAM, ARM command can be transmitted to the FPGA. The FPGA control counter related operations, the FPGA oscillator frequency 50 MHz as counter control module timing constraints, counter design with addition and subtraction counting function, power holding function, data transmission function, so as to meet the needs of the PLC controller of the count, and through the use of memory address mapping the counter controller instruction execution more efficient. The communication time sequence and communication protocol of the FPGA internal control and FPGA instruction execution controller are designed. After the simulation and testing of the design, the count frequency of a single counter reaches 2 MHz, the function of the PLC counter is basically realized, and the design requirements of the stable count are achieved.