基于Avalon-MM的I2C总线控制器设计及VMM验证

Avalon-MM Based I2C Bus Controller Design and Verification Using VMM 

摘要:

分析了Avalon-MM总线的架构以及I2C总线的传输方式,提出了一种可行的I2C总线控制设计方案,并说明了详细的实现过程；设计的基于Avalon-MM总线的I2C总线控制器可复用IP核,可以不加修改地应用在基于Altera公司产品的SOPC系统中；使用VMM验证方法学构建了多层次可复用的验证平台,对设计进行了全面的验证；整个验证平台使用systemverilog语言实现,仿真工具使用VCS-MX200606；最后仿真结果显示,设计被完全地验证并达到100%覆盖率。

Abstract:

In this paper, the architecture of Avalon-MM and the I2C bus protocol is analyzed. Then, a design of reusable I2C bus controller based on Avalon-MM bus and the detailed implement process is presented. This reusable IP core can be used in the SOPC system built on Altera company product without modification. A multi-level and reusable verification platform is implemented using VMM to verify this design. The whole verification environment uses the System Verilog language, and the simulation tool is Synopsys VCS-MX200606. The verification results indicate that design has been exactly checked out with 100% coverage. 