基于IODELAY原语SAR载荷模拟器延迟单元设计

Design of Delay Unit in SAR Load Simulator Based on IODELAY Primitive

摘要:

针对星载合成孔径雷达中数传分系统接收数据时序拉偏测试需求,本文提出一种基于FPGA原语的SAR载荷模拟器延时单元设计与实现。该延迟单元采用IODELAY原语,通过时序约束实现正反向时钟拉偏功能。仿真与试验结果表明,该延迟单元时序调整范围可达-6ns至6ns,步进1ns,系统运行稳定,满足设计要求。

Abstract:

In allusion to the requirement of timing perturbation of data transmission subsystem in spaceborne synthetic aperture radar (SAR), a new design of SAR load simulator, who is based on delay unit with FPGA primitive, is proposed in this thesis. The delay unit , who can do timing perturbation in data transmission subsystem test, consists of IODELAY primitive, and is designed by timing rules. Finally, the performance and robustness are assessed through the simulation and test, whose result shows that the range of timing perturbation is from -6ns to 6ns with 1ns step.