一种可编程全数字锁相环的设计与实现

Design and Implementation of a Programmable ADPLL

摘要:

针对传统的全数字锁相环电路参数不可调、锁相速度慢及锁相范围窄的缺点,提出了一种可编程全数字锁相环。采用电子设计自动化技术完成了该系统设计,并对所设计的电路进行了计算机仿真与分析,最后,采用FPGA予以硬件电路的实现；系统仿真与硬件实验证明,该锁相环中数字滤波器和数控振荡器的参数可以自主设定,改变数字滤波器的参数可加快锁相速度,改变数控振荡器的参数可扩大锁相范围；该锁相环具有锁相速度快、锁相范围宽、电路结构简单、参数设计灵活和易于集成等优点,可适用于许多不同用途的领域。

Abstract:

To avoid the shortcomings of traditional all digital phase-locked loop (ADPLL) on circuit parameters adjustment, low lock speed and narrow lock range, a programmable DPLL is proposed. The system design is completed by using electronic design automation(EDA) technology, while simulation and analysis of the DPLL circuit are carried through computer aided technology, and finally, the system is implemented on a FPGA hardware platform. System simulation and hardware test results verify that parameters of the digital filter and controlled oscillator of the system can be adjusted through programming, i.e. changing parameters of the digital filter leads to raising the lock speed, while changing that of the digital oscillator gives rise to broadening the lock range. The phase-locked loop is characteristic of its high lock-speed, wide lock range, simple circuit structure, flexible parameters design, and easy system integration, etc., and also it can be applied to many different areas.