基于ATE的FPGA亚稳态的激发与验证

Excitation and Validation of Metastable Behavior in FPGA Based on ATE 

摘要:

在FPGA电路设计中,信号间常发生跨时钟域的传输,亚稳态问题成为影响系统可靠性的关键因素；目前的测试方法不能满足对亚稳态的测试,如何有效地激发亚稳态及验证亚稳态保护措施的有效性,成为FPGA测试的关键问题；文章详细分析了FPGA中亚稳态产生的根源,基于ATE测试系统,提出了一种有效的多时钟域的测试方法,通过设计输入信号间的时序偏差,激发亚稳态,并验证电路相应的保护措施是否有效；在此基础上,设计了基于ATE的测试系统,调整时钟间隔,成功的激发出亚稳态,并验证了经过两级同步后的电路有效地避免了亚稳态的传播。

Abstract:

Signals often transmit across different clock domains in FPGA circuit design, which may result in metastable state when asynchronous inputs have critical timing combinations. Metastable issues become a key factor in digital system design and reliability analysis. Because of no methods can meet the test of metastable, how to effectively stimulate metastable and verify the validity of metastable protection measures is becoming a key issue in FPGA testing. Here, we analyzed the metastable behavior and their relevance to digital systems, and proposed a way to test multiple clock domains based on ATE test system, through the design of the deviation between the input timing signals to stimulate metastable, and verify whether the circuit protection is valid or not. On this basis, designed the ATE test system, changed the clock interval, excited the metastable behavior successfully and verified the synchronized circuits effectively avoid the spread of metastable state.