基于FPGA自主控制浮点加减乘除控制器设计

Design of Floating Point Multiplication Controller of Independent Control Based on FPGA

摘要:

为实现一种能够自主完成浮点数加/减、乘、除运算功能的浮点数算术运算执行控制器,提出了一种基于采用FPGA的并行操作设计硬连接的浮点算术运算控制电路及其时序控制方法,该控制器能够自动选择运算器,调整内部时序脉冲的时钟周期,自主完成操作数的配置并进行浮点数加/减、乘、法运算的功能,运算结果读到系统数据总线；论述了该控制器的电路构成和基本原理,分析操作数配置与运算器的选择,及内部时序脉冲作用下的执行过程,应用Verilog HDL语言实现相关硬件的构建和连接；通过仿真综合测试可知,该控制器的最高频率可达132.426 M,从输入端口到输出端口的延时数据为:最小延时是5.367 ns,最大延时是18.347 ns,耗用的IO输入输出端口占总资源的31.45%；并能够自动选择运算器,自主完成相应的算术运算。

Abstract:

In order to achieve an execution controller which can complete the Plus/minus, multiply and divide floating point calculation function independently, this paper proposes a parallel operation based on the FPGA circuit hard-wired floating-point number operation control circuit and the sequential control method. The controller can automatically select arithmetic unit, adjust the internal clock of the sequential pulse cycle,independently complete configuration of the operands and the function of floating-point addition/subtraction, multiplication operation,. operation results transmitted to the system data bus. Discusses the circuit of the controller structure and basic principle, analyzes the operand configuration and the choice of the arithmetic unit under the action of execution. VerilogHDL language is applied to implement the building and related hardware connection. After the completion of the design the simulation test shows that the single instruction controller can independently complete the floating-point Plus/minus, multiply and divide. 