基于CPLD的自适应高精度时统模块设计

Design of Adaptive and High Precision Time System Based on CPLD

摘要:

通过分析影响时统模块自守时精度的因素,给出传统时统模块自守时精度低的原因,提出了基于CPLD的自适应高精度时统模块的硬件设计和CPLD逻辑设计方法；通过仿真及实际测试结果表明,基于CPLD的自适应高精度时统模块的自守时时钟与参考时钟的误差每小时小于3.6 ms,并且根据自守时精度的数学模型,通过提高晶振的频率可以提高模块的自守时精度。

Abstract:

Analyzing the diathesis of affecting timing system’s timekeeping precision,the reason of timekeeping low precision has been presented. The hardware and CPLD logic design of adaptive and high precision time system based CPLD has been put forward. By the result of testing and emulating, the inaccuracy of the timekeeping clock and the reference clock is less than 3.6ms/h. The mathematical model indicates that the precision of timekeeping can be improved by increasing the frequency of crystalloid.