基于FPGA自主控制浮点加减控制器设计

Design of Floating Point Add and Subtract Controller of Independent Control Based on FPGA

摘要:

为实现一种能够自主完成浮点数加/减运算功能的浮点数加/减运算执行控制器,提出了一种基于采用FPGA并行操作电路硬连接的浮点数加/减运算控制电路及其时序控制方法；该控制器在接收到操作数类型与参与运算的操作数后,在内部时序脉冲作用下,可以自主完成操作数的配置以及浮点数加/减法运算的功能,运算结果传输到系统数据总线；论述了该控制器的电路构成和基本原理,分析操作数类型与操作数在内部时序脉冲作用下的执行过程,应用Verilog HDL语言实现相关硬件的构建和连接；设计完成后通过仿真测试可知,该控制器运行的最高频率可达178.317 M,从输入端口到输出端口的延时数据为:最小延时是3.185 ns,最大延时是15.336 ns,耗用的IO输入输出端口占总资源的27.92%,数据表明该控制器提高了运算器的运算速度,且能够自主完成浮点数加/减运算。

Abstract:

In order to achieve the plus/minus floating point calculation function independently by on execution controller, this paper proposes a parallel operation based on the FPGA circuit hard-wired floating-point number plus/minus operation control circuit and the sequential control method. The controller can independently complete much floating-point addition and subtraction operation function of the process of operation under the influence of internal timing pluse when it receives the operand type and multioperand. operation results transmitted to the system data bus. Discusses the circuit of the controller structure and basic principle, analyzes the operand type and multioperand in internal temporal pulse under the action of execution. VerilogHDL language is applied to implement the building and related hardware connection. After the completion of the design the simulation test shows that Maximum delay is 15.336 ns, consumption of IO input/output port of total resources 27.92%, data show that the controller can improve the arithmetic unit operation speed when performing more operands floating-point addition and subtraction,