基于FPGA的PLC数据输出控制IP核设计

Design of Data Output control IP Core in PLC Based on FPGA

摘要:

提出应用FPGA设计PLC数据输出控制IP核的思路。该IP核执行输出数据相关命令时,在内部时序脉冲控制下按照Y编号地址自主完成数据在存储单元的寻址和读写操作；论述了控制器的工作原理和电路设计,应用Verilog语言实现硬件电路的构建及功能；测试表明:该IP核可以自主完成对数据处理和输出要求,使数据输出与系统其它功能模块实现并行处理,提高了PLC运行速度。

Abstract:

This paper proposed a method which employ FPGA to design PLC data output control IP core.By the control of internal timing pulse, the controller will accomplish the informatiom's addressing and read/write operations in storage unit with Y numbered address independently while the controller carrying out the output information command.This paper discusses the circuit composition and basic principle of the IP core.Using Verilog HDL language to implement the construction and the function of the hardware circuit.The test result shows that:while the PLC user program is running,the controller can read or write the data information according to the command independently,making the execution of the output data information command and other system function module in parallel operation to improve the speed of PLC instruction execution sequence.