基于LabVIEW FPGA的三相锁相环设计与实现

Realization and Design of A Three Phase Phase-locked Loop Based on LabVIEW FPGA

摘要:

针对传统FPGA模式开发的锁相环在实时人机交互方面的不足,设计了基于LabVIEW FPGA技术的三相锁相环;方案以sbRIO-9631模块为硬件平台,利用LabVIEW编程控制FPGA逻辑,在FPGA中分三级流水线实现了基于dq变换的锁相环算法,并通过FIFO实时上传采集信号、锁定相位至PC机,最后在PC机上实现对锁相环性能分析、PI参数调控和数据显示；经过实验,该锁相环具有较高的精度,锁相时间约为两个周期,锁相误差约为0.03 rad,通过PC机可实时调节锁相性能。

Abstract:

A three phase phase-locked loop (PPL) based on LabVIEW FPGA structure is proposed, to make up the shortages of real-time human-machine interaction based on traditional FPGA model. The solution is designed on sbRIO-9631 platform, use LabVIEW program to control FPGA logic. Adopt three pipelines to implement the improved synchronous transform in FPGA program, and besides, use FIFO to translate acquired signal and output-phase from FPGA to PC. At last, achieve the PLL performance analysis, real-time display and PI parameters setting functions in PC. Experimental results show that the PLL has a phase-locked time with tow cycles and a phase-locked lag with 0.03 rad, it not only has a good phase-locked precision, but also has a well real-time human-machine interaction.