基于FPGA的PLC位信息输出控制器设计

Design of Bit Information Output Controller in PLC Based on FPGA 

摘要:

提出应用FPGA设计PLC位信息输出与读取控制器的思路。该控制器执行输出位信息相关命令时,在内部时序脉冲控制下按照Y编号地址自主完成位信息在位存储单元的寻址和读写操作；论述了控制器的电路构成和基本原理,应用Verilog HDL语言实现硬件电路的构建与连接；测试表明,该控制器在PLC用户程序执行过程中可以自主将位信息按要求输出和读取,使输出位信息命令的执行与系统其它功能模块实现并行处理,提高了PLC执行指令序列的速度,缩短了PLC扫描周期。

Abstract:

This paper proposed a method which employed FPGA to design PLC information output and read controller.By the control of internal timing pulse, the controller will accomplish the bit informatiom's addressing and read/write operations in storage unit with Y numbered address independently while the controller carrying out the output information command.This paper discusses the circuit composition and basic principle of the controller.Using Verilog HDL language to implement the construction and the connection of the hardware circuit.The test result shows that:while the PLC user program is running,the controller can read or write the bit information according to the command independently,making the execution of the output bit information command and other system function module in parallel operation to improve the speed of PLC instruction execution sequence, shorten the PLC scan cycle.