基于路径相关性的电路小延时缺陷检测算法

Circuit Small Delay Defects Detection Algorithm Based on Path Correlation

摘要:

在基于纳米技术的现代电路中,小延时缺陷(SDDs)检测是个重要问题,即使这些SDD缺陷没有导致功能性故障,但也是一种可靠性隐患,如果工艺发生变化,这些缺陷的检测更为困难；文章提出一种基于电路路径延时相关性的SDD缺陷检测算法,即使工艺发生变化也可以检测出SDD缺陷；该算法利用了如下原理:对两个高度相关的路径,一条路径的延时方差的重要部分可以用另一条路径的延时方差进行描述；另外,考虑了空间和结构相关性及随机掺杂波动,开发并部署了一种统计学计时分析框架,以计算时间信息和跨径相关性(IPC)；基于74LS85和ISCAS85基准电路的仿真结果验证了算法的可行性。

Abstract:

Detection of Small Delay Defects (SDDs) is a major concern in modern circuits using nanometer technologies, even when SDDs do not produce functional failures, they represent a reliability risk. The detection of these defects aggravates in the presence of process variations. In this paper, a methodology to detect SDDs in the presence of process variations using delay correlation information between paths of a circuit is proposed. This methodology exploits the concept that for two highly correlated paths, an important part of the delay variance in one path can be described by the delay variance in the second path. In addition, a statistical timing analysis framework has been developed and implemented to compute timing information and Inter-Path Correlation (IPC), which considers the spatial and structural correlation, and random dopant fluctuations. Simulation results in 74LS85 and ISCAS85 benchmark circuits evince the feasibility of the proposed methodology.